Semiconductor memory arrays are conventionally classified into two types, namely read only memories (ROM) and random access memories (RAM) Random access memories are themselves sub-classified into two main types, namely static memories (SRAM) and dynamic memories (DRAM).
A majority of memory arrays of all types require the use of a so-called sense amplifier which responds either to the difference in potential on two complementary bit lines, or occasionally the difference between the potential on a single bit line and that on a reference bit line to evaluate the content of a particular memory location. Again, such sense amplifiers are classifiable into two types, namely static sense amplifiers--in which a direct current path exists between positive and negative supply terminals--and dynamic sense amplifiers--in which only transient paths exist for current flow.
As is known to those skilled in the art, evaluation of memory content usually takes place at specific instance of time related to a clock cycle in the system and the value which is sensed must be retained for a substantial period of time after such evaluation to allow for circuitry downstream of the memory to receive, and act upon, the correct values.
In conventional dynamic sense amplifiers a latch is provided, conventionally of cross-coupled NAND gates, to store the last value sensed by the sense amplifier until the time comes for a new value to be sensed and output to the latch.
Such an arrangement is wasteful of chip area and also slows down the performance of the memory since allowance must be made for two gate delays before the output has achieved a stable level.
It is accordingly an object of the present invention to provide a dynamic sense amplifier which at least partially mitigates the difficulties of the prior art.
It is a secondary object of the invention to provide a dynamic sense amplifier having an output which is capable of being rendered high impedance, thus adopting a tristate condition so as to avoid affecting downstream circuit elements.